`include "ysyx_23060189_cpu.svh"
`include "ysyx_23060189_isa.svh"

module ysyx_23060189(
  // input  wire clock,
  // // input  wire clk_mem,
  // input  wire reset,
  // output wire done,
  // // input  wire [`ysyx_23060189_DataBus]   inst,
  // output wire [`ysyx_23060189_AddrBus]   addr

  input  wire        clock,
  input  wire        reset,
  input  wire        io_interrupt,

  /* AXI4 master interface */
  input  wire        io_master_awready,
  output wire        io_master_awvalid,
  output wire [31:0] io_master_awaddr,
  output wire [ 3:0] io_master_awid,
  output wire [ 7:0] io_master_awlen,
  output wire [ 2:0] io_master_awsize,
  output wire [ 1:0] io_master_awburst,
  input  wire        io_master_wready,
  output wire        io_master_wvalid,
  output wire [31:0] io_master_wdata,
  output wire [ 3:0] io_master_wstrb,
  output wire        io_master_wlast,
  output wire        io_master_bready,
  input  wire        io_master_bvalid,
  input  wire [ 1:0] io_master_bresp,
  input  wire [ 3:0] io_master_bid,
  input  wire        io_master_arready,
  output wire        io_master_arvalid,
  output wire [31:0] io_master_araddr,
  output wire [ 3:0] io_master_arid,
  output wire [ 7:0] io_master_arlen,
  output wire [ 2:0] io_master_arsize,
  output wire [ 1:0] io_master_arburst,
  output wire        io_master_rready,
  input  wire        io_master_rvalid,
  input  wire [ 1:0] io_master_rresp,
  input  wire [31:0] io_master_rdata,
  input  wire        io_master_rlast,
  input  wire [ 3:0] io_master_rid,

  /* AXI4 slave interface */
  output wire        io_slave_awready,
  input  wire        io_slave_awvalid,
  input  wire [31:0] io_slave_awaddr,
  input  wire [ 3:0] io_slave_awid,
  input  wire [ 7:0] io_slave_awlen,
  input  wire [ 2:0] io_slave_awsize,
  input  wire [ 1:0] io_slave_awburst,
  output wire        io_slave_wready,
  input  wire        io_slave_wvalid,
  input  wire [31:0] io_slave_wdata,
  input  wire [ 3:0] io_slave_wstrb,
  input  wire        io_slave_wlast,
  input  wire        io_slave_bready,
  output wire        io_slave_bvalid,
  output wire [ 1:0] io_slave_bresp,
  output wire [ 3:0] io_slave_bid,
  output wire        io_slave_arready,
  input  wire        io_slave_arvalid,
  input  wire [31:0] io_slave_araddr,
  input  wire [ 3:0] io_slave_arid,
  input  wire [ 7:0] io_slave_arlen,
  input  wire [ 2:0] io_slave_arsize,
  input  wire [ 1:0] io_slave_arburst,
  input  wire        io_slave_rready,
  output wire        io_slave_rvalid,
  output wire [ 1:0] io_slave_rresp,
  output wire [31:0] io_slave_rdata,
  output wire        io_slave_rlast,
  output wire [ 3:0] io_slave_rid
);
  wire done;

  // assign io_master_awvalid = 0;
  // assign io_master_awaddr  = 0;
  // assign io_master_awid    = 0;
  // assign io_master_awlen   = 0;
  // assign io_master_awsize  = 0;
  // assign io_master_awburst = 0;
  // assign io_master_wvalid  = 0;
  // assign io_master_wdata   = 0;
  // assign io_master_wstrb   = 0;
  // assign io_master_wlast   = 0;
  // assign io_master_bready  = 0;
  // assign io_master_arvalid = 0;
  // assign io_master_araddr  = 0;
  // assign io_master_arid    = 0;
  // assign io_master_arlen   = 0;
  // assign io_master_arsize  = 0;
  // assign io_master_arburst = 0;
  // assign io_master_rready  = 0;

  /* AXI4 slave interface */
  assign io_slave_awready = 0;
  assign io_slave_wready  = 0;
  assign io_slave_bvalid  = 0;
  assign io_slave_bresp   = 0;
  assign io_slave_bid     = 0;
  assign io_slave_arready = 0;
  assign io_slave_rvalid  = 0;
  assign io_slave_rresp   = 0;
  assign io_slave_rdata   = 0;
  assign io_slave_rlast   = 0;
  assign io_slave_rid     = 0;

  /* IFU <=> SRAM */
  wire                             inst_valid;
  wire                             read;

  /* data: IFU <=> IDU */
  wire [`ysyx_23060189_DataBus]    if_inst;
  wire [`ysyx_23060189_DataBus]    if_pc;
  wire [`ysyx_23060189_RegAddrBus] if_wb_addr;
  wire [`ysyx_23060189_DataBus]    if_rs1_data;
  wire [`ysyx_23060189_DataBus]    if_rs2_data;

  wire                             if_valid;
  wire                             de_ready;

  /* data: IDU <=> EXU */
  wire [`ysyx_23060189_DataBus]    de_inst;
  wire [`ysyx_23060189_DataBus]    de_pc;
  wire [`ysyx_23060189_PcSelBus]   de_PC_sel;
  wire [`ysyx_23060189_ImmSelBus]  de_Imm_sel;
  wire [`ysyx_23060189_AluOpBus]   de_Alu_op;
  wire [`ysyx_23060189_StTypeBus]  de_st_type;
  wire [`ysyx_23060189_LdTypeBus]  de_ld_type;
  wire [`ysyx_23060189_BrTypeBus]  de_br_type;
  wire [`ysyx_23060189_AluSelBus]  de_A_sel;
  wire [`ysyx_23060189_AluSelBus]  de_B_sel;
  wire [`ysyx_23060189_WbSelBus]   de_wb_sel;
  wire [`ysyx_23060189_CsrTypeBus] de_csr_cmd;
  wire                             de_wb_en;
  wire [`ysyx_23060189_RegAddrBus] de_wb_addr;
  wire [`ysyx_23060189_DataBus]    de_rs1_data;
  wire [`ysyx_23060189_DataBus]    de_rs2_data;

  wire                             de_valid;
  wire                             ex_ready;

  /* data: EXU <=> MEU */
  wire [`ysyx_23060189_DataBus]    ex_inst;
  wire [`ysyx_23060189_DataBus]    ex_pc;
  wire [`ysyx_23060189_PcSelBus]   ex_PC_sel;
  wire [`ysyx_23060189_StTypeBus]  ex_st_type;
  wire [`ysyx_23060189_LdTypeBus]  ex_ld_type;
  wire [`ysyx_23060189_WbSelBus]   ex_wb_sel;
  wire [`ysyx_23060189_CsrTypeBus] ex_csr_cmd;
  wire                             ex_wb_en;
  wire                             ex_br_taken;
  wire [`ysyx_23060189_DataBus]    ex_Alu_out;
  wire [`ysyx_23060189_RegAddrBus] ex_wb_addr;
  wire [`ysyx_23060189_DataBus]    ex_rs2_data;

  wire                             ex_valid;
  wire                             me_ready;

  /* data: MEU <=> WBU */
  wire [`ysyx_23060189_DataBus]    me_inst;
  wire [`ysyx_23060189_DataBus]    me_pc;
  wire [`ysyx_23060189_PcSelBus]   me_PC_sel;
  wire [`ysyx_23060189_WbSelBus]   me_wb_sel;
  wire [`ysyx_23060189_CsrTypeBus] me_csr_cmd;
  wire                             me_wb_en;
  wire                             me_br_taken;
  wire [`ysyx_23060189_DataBus]    me_Alu_out;
  wire [`ysyx_23060189_RegAddrBus] me_wb_addr;
  wire [`ysyx_23060189_DataBus]    me_rd_data;

  wire                             me_valid;
  wire                             wb_ready;

  /* data: WBU => IFU */
  wire [`ysyx_23060189_PcSelBus]   wb_PC_sel;
  wire [`ysyx_23060189_WbSelBus]   wb_wb_sel;
  wire                             wb_wb_en;
  wire                             wb_br_taken;
  wire [`ysyx_23060189_DataBus]    wb_csr_out;
  wire [`ysyx_23060189_DataBus]    wb_Alu_out;
  wire [`ysyx_23060189_RegAddrBus] wb_wb_addr;
  wire [`ysyx_23060189_DataBus]    wb_rd_data;

  wire                             wb_valid;
  wire                             if_ready;

  /* data:MEU <=> MEM */
  wire [`ysyx_23060189_DataBus]   mem_addr;
  wire [`ysyx_23060189_StTypeBus] st_type;
  wire [`ysyx_23060189_LdTypeBus] ld_type;
  wire [`ysyx_23060189_DataBus]   wr_data;
  wire [`ysyx_23060189_DataBus]   rd_data;
  wire                            meu_valid;
  wire                            mem_valid;

  /* data:MEM <=> Master 1 interface */
  wire                            mem_to_master_ren;
  wire [`ysyx_23060189_AddrBus]   mem_to_master_raddr;
  wire [2:0]                      mem_to_master_arsize;
  wire [`ysyx_23060189_DataBus]   mem_to_master_rdata;
  wire                            mem_to_master_rvalid;
  wire                            mem_to_master_wen;
  wire [`ysyx_23060189_AddrBus]   mem_to_master_waddr;
  wire [`ysyx_23060189_DataBus]   mem_to_master_wdata;
  wire [7:0]                      mem_to_master_wmask;
  wire [2:0]                      mem_to_master_awsize;
  wire                            mem_to_master_wdone;

  /* data:Master interface <=> Master 2 interface of Arbiter */
  // Write address channel
  wire                            mem_to_arbiter_AWVALID;
  wire                            mem_to_arbiter_AWREADY;
  wire [`ysyx_23060189_AddrBus]   mem_to_arbiter_AWADDR;
  // wire [2 : 0]                    mem_to_arbiter_AWPROT;
  wire [3:0]                      mem_to_arbiter_AWID;
  wire [7:0]                      mem_to_arbiter_AWLEN;
  wire [2:0]                      mem_to_arbiter_AWSIZE;
  wire [1:0]                      mem_to_arbiter_AWBURST;
  // Write data channel
  wire                            mem_to_arbiter_WVALID;
  wire                            mem_to_arbiter_WREADY;
  wire [`ysyx_23060189_DataBus]   mem_to_arbiter_WDATA;
  wire [3:0]                      mem_to_arbiter_WSTRB;
  wire                            mem_to_arbiter_WLAST;
  // Write response channel
  wire                            mem_to_arbiter_BVALID;
  wire                            mem_to_arbiter_BREADY;
  wire [1:0]                      mem_to_arbiter_BRESP;
  wire [3:0]                      mem_to_arbiter_BID;
  // Read address channel
  wire                            mem_to_arbiter_ARVALID;
  wire                            mem_to_arbiter_ARREADY;
  wire [`ysyx_23060189_AddrBus]   mem_to_arbiter_ARADDR;
  // wire [2 : 0]                    mem_to_arbiter_ARPROT;
  wire [3:0]                      mem_to_arbiter_ARID;
  wire [7:0]                      mem_to_arbiter_ARLEN;
  wire [2:0]                      mem_to_arbiter_ARSIZE;
  wire [1:0]                      mem_to_arbiter_ARBURST;
  // Read data channel
  wire                            mem_to_arbiter_RVALID;
  wire                            mem_to_arbiter_RREADY;
  wire [`ysyx_23060189_DataBus]   mem_to_arbiter_RDATA;
  wire [1:0]                      mem_to_arbiter_RRESP;
  wire                            mem_to_arbiter_RLAST;
  wire [3:0]                      mem_to_arbiter_RID;

  /* data:IFU <=> Master 2 interface */
  wire                            ifu_to_master_ren;
  wire [`ysyx_23060189_AddrBus]   ifu_to_master_raddr;
  wire [2:0]                      ifu_to_master_arsize;
  wire [`ysyx_23060189_DataBus]   ifu_to_master_rdata;
  wire                            ifu_to_master_rvalid;
  wire                            ifu_to_master_wen;
  wire [`ysyx_23060189_AddrBus]   ifu_to_master_waddr;
  wire [`ysyx_23060189_DataBus]   ifu_to_master_wdata;
  wire [7:0]                      ifu_to_master_wmask;
  wire [2:0]                      ifu_to_master_awsize;
  wire                            ifu_to_master_wdone;

  /* data:Master interface <=> Master 1 interface of Arbiter */
  // Write address channel
  wire                            ifu_to_arbiter_AWVALID;
  wire                            ifu_to_arbiter_AWREADY;
  wire [`ysyx_23060189_AddrBus]   ifu_to_arbiter_AWADDR;
  // wire [2 : 0]                    ifu_to_arbiter_AWPROT;
  wire [3:0]                      ifu_to_arbiter_AWID;
  wire [7:0]                      ifu_to_arbiter_AWLEN;
  wire [2:0]                      ifu_to_arbiter_AWSIZE;
  wire [1:0]                      ifu_to_arbiter_AWBURST;
  // Write data channel
  wire                            ifu_to_arbiter_WVALID;
  wire                            ifu_to_arbiter_WREADY;
  wire [`ysyx_23060189_DataBus]   ifu_to_arbiter_WDATA;
  wire [3:0]                      ifu_to_arbiter_WSTRB;
  wire                            ifu_to_arbiter_WLAST;
  // Write response channel
  wire                            ifu_to_arbiter_BVALID;
  wire                            ifu_to_arbiter_BREADY;
  wire [1:0]                      ifu_to_arbiter_BRESP;
  wire [3:0]                      ifu_to_arbiter_BID;
  // Read address channel
  wire                            ifu_to_arbiter_ARVALID;
  wire                            ifu_to_arbiter_ARREADY;
  wire [`ysyx_23060189_AddrBus]   ifu_to_arbiter_ARADDR;
  // wire [2 : 0]                    ifu_to_arbiter_ARPROT;
  wire [3:0]                      ifu_to_arbiter_ARID;
  wire [7:0]                      ifu_to_arbiter_ARLEN;
  wire [2:0]                      ifu_to_arbiter_ARSIZE;
  wire [1:0]                      ifu_to_arbiter_ARBURST;
  // Read data channel
  wire                            ifu_to_arbiter_RVALID;
  wire                            ifu_to_arbiter_RREADY;
  wire [`ysyx_23060189_DataBus]   ifu_to_arbiter_RDATA;
  wire [1:0]                      ifu_to_arbiter_RRESP;
  wire                            ifu_to_arbiter_RLAST;
  wire [3:0]                      ifu_to_arbiter_RID;

  /* data:Slave 1 interface of Arbiter <=> Xbar  */
  // Write address channel
  wire                            arbiter_to_xbar_AWVALID;
  wire                            arbiter_to_xbar_AWREADY;
  wire [`ysyx_23060189_AddrBus]   arbiter_to_xbar_AWADDR;
  wire [2:0]                      arbiter_to_xbar_AWPROT;
  // Write data channel
  wire                            arbiter_to_xbar_WVALID;
  wire                            arbiter_to_xbar_WREADY;
  wire [`ysyx_23060189_DataBus]   arbiter_to_xbar_WDATA;
  wire [3:0]                      arbiter_to_xbar_WSTRB;
  // Write response channel
  wire                            arbiter_to_xbar_BVALID;
  wire                            arbiter_to_xbar_BREADY;
  wire [1:0]                      arbiter_to_xbar_BRESP;
  // Read address channel
  wire                            arbiter_to_xbar_ARVALID;
  wire                            arbiter_to_xbar_ARREADY;
  wire [`ysyx_23060189_AddrBus]   arbiter_to_xbar_ARADDR;
  wire [2:0]                      arbiter_to_xbar_ARPROT;
  // Read data channel
  wire                            arbiter_to_xbar_RVALID;
  wire                            arbiter_to_xbar_RREADY;
  wire [`ysyx_23060189_DataBus]   arbiter_to_xbar_RDATA;
  wire [1:0]                      arbiter_to_xbar_RRESP;

  /* data:Xbar <=> dsram  */
  // Write address channel
  wire                            xbar_to_dsram_AWVALID;
  wire                            xbar_to_dsram_AWREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_dsram_AWADDR;
  wire [2:0]                      xbar_to_dsram_AWPROT;
  // Write data channel
  wire                            xbar_to_dsram_WVALID;
  wire                            xbar_to_dsram_WREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_dsram_WDATA;
  wire [3:0]                      xbar_to_dsram_WSTRB;
  // Write response channel
  wire                            xbar_to_dsram_BVALID;
  wire                            xbar_to_dsram_BREADY;
  wire [1:0]                      xbar_to_dsram_BRESP;
  // Read address channel
  wire                            xbar_to_dsram_ARVALID;
  wire                            xbar_to_dsram_ARREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_dsram_ARADDR;
  wire [2:0]                      xbar_to_dsram_ARPROT;
  // Read data channel
  wire                            xbar_to_dsram_RVALID;
  wire                            xbar_to_dsram_RREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_dsram_RDATA;
  wire [1:0]                      xbar_to_dsram_RRESP;

  /* data:Xbar <=> uart  */
  // Write address channel
  wire                            xbar_to_uart_AWVALID;
  wire                            xbar_to_uart_AWREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_uart_AWADDR;
  wire [2:0]                      xbar_to_uart_AWPROT;
  // Write data channel
  wire                            xbar_to_uart_WVALID;
  wire                            xbar_to_uart_WREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_uart_WDATA;
  wire [3:0]                      xbar_to_uart_WSTRB;
  // Write response channel
  wire                            xbar_to_uart_BVALID;
  wire                            xbar_to_uart_BREADY;
  wire [1:0]                      xbar_to_uart_BRESP;
  // Read address channel
  wire                            xbar_to_uart_ARVALID;
  wire                            xbar_to_uart_ARREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_uart_ARADDR;
  wire [2:0]                      xbar_to_uart_ARPROT;
  // Read data channel
  wire                            xbar_to_uart_RVALID;
  wire                            xbar_to_uart_RREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_uart_RDATA;
  wire [1:0]                      xbar_to_uart_RRESP;

  /* data:Xbar <=> clint  */
  // Write address channel
  wire                            xbar_to_clint_AWVALID;
  wire                            xbar_to_clint_AWREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_clint_AWADDR;
  wire [2:0]                      xbar_to_clint_AWPROT;
  // Write data channel
  wire                            xbar_to_clint_WVALID;
  wire                            xbar_to_clint_WREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_clint_WDATA;
  wire [3:0]                      xbar_to_clint_WSTRB;
  // Write response channel
  wire                            xbar_to_clint_BVALID;
  wire                            xbar_to_clint_BREADY;
  wire [1:0]                      xbar_to_clint_BRESP;
  // Read address channel
  wire                            xbar_to_clint_ARVALID;
  wire                            xbar_to_clint_ARREADY;
  wire [`ysyx_23060189_AddrBus]   xbar_to_clint_ARADDR;
  wire [2:0]                      xbar_to_clint_ARPROT;
  // Read data channel
  wire                            xbar_to_clint_RVALID;
  wire                            xbar_to_clint_RREADY;
  wire [`ysyx_23060189_DataBus]   xbar_to_clint_RDATA;
  wire [1:0]                      xbar_to_clint_RRESP;

  /* data:Slave interface <=> UART */
  wire                            slave_to_uart_ren;
  wire [`ysyx_23060189_AddrBus]   slave_to_uart_raddr;
  wire [`ysyx_23060189_DataBus]   slave_to_uart_rdata;
  wire                            slave_to_uart_rvalid;

  wire                            slave_to_uart_wen;
  wire [`ysyx_23060189_AddrBus]   slave_to_uart_waddr;
  wire [`ysyx_23060189_DataBus]   slave_to_uart_wdata;
  wire [7:0]                      slave_to_uart_wmask;
  wire                            slave_to_uart_wdone;

  /* data:Slave interface <=> DSRAM */
  wire                            slave_to_dsram_ren;
  wire [`ysyx_23060189_AddrBus]   slave_to_dsram_raddr;
  wire [`ysyx_23060189_DataBus]   slave_to_dsram_rdata;
  wire                            slave_to_dsram_rvalid;

  wire                            slave_to_dsram_wen;
  wire [`ysyx_23060189_AddrBus]   slave_to_dsram_waddr;
  wire [`ysyx_23060189_DataBus]   slave_to_dsram_wdata;
  wire [7:0]                      slave_to_dsram_wmask;
  wire                            slave_to_dsram_wdone;

  /* data:Slave interface <=> CLINT */
  wire                            slave_to_clint_ren;
  wire [`ysyx_23060189_AddrBus]   slave_to_clint_raddr;
  wire [`ysyx_23060189_DataBus]   slave_to_clint_rdata;
  wire                            slave_to_clint_rvalid;

  wire                            slave_to_clint_wen;
  wire [`ysyx_23060189_AddrBus]   slave_to_clint_waddr;
  wire [`ysyx_23060189_DataBus]   slave_to_clint_wdata;
  wire [7:0]                      slave_to_clint_wmask;
  wire                            slave_to_clint_wdone;

  // assign addr = if_pc;

  // MEM
  ysyx_23060189_Mem mem(
    .ACLK      (clock),
    .ARESETn   (~reset),
    // Mem <=> Master interface
    .ren       (mem_to_master_ren),
    .raddr     (mem_to_master_raddr),
    .arsize    (mem_to_master_arsize),
    .rdata     (mem_to_master_rdata),
    .rvalid    (mem_to_master_rvalid),
    .wen       (mem_to_master_wen),
    .waddr     (mem_to_master_waddr),
    .wdata     (mem_to_master_wdata),
    .wmask     (mem_to_master_wmask),
    .awsize    (mem_to_master_awsize),
    .wdone     (mem_to_master_wdone),
    // MEU <=> Mem
    .meu_valid (meu_valid),
    .addr      (mem_addr),
    .st_type   (st_type),
    .ld_type   (ld_type),
    .wr_data   (wr_data),
    .rd_data   (rd_data),
    .mem_valid (mem_valid)
  );

  // master2 interface: MEM <=> Arbiter
  ysyx_23060189_AXI4_master mem_to_arbiter_master_interface(
    /* Master <=> Master interface */
    .ren     (mem_to_master_ren),
    .raddr   (mem_to_master_raddr),
    .arsize  (mem_to_master_arsize),
    .rdata   (mem_to_master_rdata),
    .rvalid  (mem_to_master_rvalid),

    .wen     (mem_to_master_wen),
    .waddr   (mem_to_master_waddr),
    .wdata   (mem_to_master_wdata),
    .wmask   (mem_to_master_wmask),
    .awsize  (mem_to_master_awsize),
    .wdone   (mem_to_master_wdone),

    /* Master interface <=> Arbiter */
    // Global
    .ACLK    (clock),
    .ARESETn (~reset),

    // Write address channel
    .AWVALID (mem_to_arbiter_AWVALID),
    .AWREADY (mem_to_arbiter_AWREADY),
    .AWADDR  (mem_to_arbiter_AWADDR),
    .AWID    (mem_to_arbiter_AWID),
    .AWLEN   (mem_to_arbiter_AWLEN),
    .AWSIZE  (mem_to_arbiter_AWSIZE),
    .AWBURST (mem_to_arbiter_AWBURST),

    // Write data channel
    .WVALID  (mem_to_arbiter_WVALID),
    .WREADY  (mem_to_arbiter_WREADY),
    .WDATA   (mem_to_arbiter_WDATA),
    .WSTRB   (mem_to_arbiter_WSTRB),
    .WLAST   (mem_to_arbiter_WLAST),

    // Write response channel
    .BVALID  (mem_to_arbiter_BVALID),
    .BREADY  (mem_to_arbiter_BREADY),
    .BRESP   (mem_to_arbiter_BRESP),
    .BID     (mem_to_arbiter_BID),

    // Read address channel
    .ARVALID (mem_to_arbiter_ARVALID),
    .ARREADY (mem_to_arbiter_ARREADY),
    .ARADDR  (mem_to_arbiter_ARADDR),
    .ARID    (mem_to_arbiter_ARID),
    .ARLEN   (mem_to_arbiter_ARLEN),
    .ARSIZE  (mem_to_arbiter_ARSIZE),
    .ARBURST (mem_to_arbiter_ARBURST),

    // Read data channel
    .RVALID  (mem_to_arbiter_RVALID),
    .RREADY  (mem_to_arbiter_RREADY),
    .RDATA   (mem_to_arbiter_RDATA),
    .RRESP   (mem_to_arbiter_RRESP),
    .RLAST   (mem_to_arbiter_RLAST),
    .RID     (mem_to_arbiter_RID)
  );

  // slave interface: MEM <=> DSRAM
  // ysyx_23060189_AXI_Lite_slave xbar_to_dsram_slave_interface(
  //   /* Slave <=> Slave interface */
  //   .ren(slave_to_dsram_ren),
  //   .raddr(slave_to_dsram_raddr),
  //   .rdata(slave_to_dsram_rdata),
  //   .rvalid(slave_to_dsram_rvalid),
  //
  //   .wen(slave_to_dsram_wen),
  //   .waddr(slave_to_dsram_waddr),
  //   .wdata(slave_to_dsram_wdata),
  //   .wmask(slave_to_dsram_wmask),
  //   .wdone(slave_to_dsram_wdone),
  //
  //   /* Slave interface <=> Arbiter */
  //   // Global
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   // Write address channel
  //   .AWVALID(xbar_to_dsram_AWVALID),
  //   .AWREADY(xbar_to_dsram_AWREADY),
  //   .AWADDR(xbar_to_dsram_AWADDR),
  //   .AWPROT(xbar_to_dsram_AWPROT),
  //
  //   // Write data channel
  //   .WVALID(xbar_to_dsram_WVALID),
  //   .WREADY(xbar_to_dsram_WREADY),
  //   .WDATA(xbar_to_dsram_WDATA),
  //   .WSTRB(xbar_to_dsram_WSTRB),
  //
  //   // Write response channel
  //   .BVALID(xbar_to_dsram_BVALID),
  //   .BREADY(xbar_to_dsram_BREADY),
  //   .BRESP(xbar_to_dsram_BRESP),
  //
  //   // Read address channel
  //   .ARVALID(xbar_to_dsram_ARVALID),
  //   .ARREADY(xbar_to_dsram_ARREADY),
  //   .ARADDR(xbar_to_dsram_ARADDR),
  //   .ARPROT(xbar_to_dsram_ARPROT),
  //
  //   // Read data channel
  //   .RVALID(xbar_to_dsram_RVALID),
  //   .RREADY(xbar_to_dsram_RREADY),
  //   .RDATA(xbar_to_dsram_RDATA),
  //   .RRESP(xbar_to_dsram_RRESP)
  // );

  ysyx_23060189_AXI4_arbiter arbiter (
    // Global
    .ACLK             (clock),
    .ARESETn          (~reset),

    /* Master1 interface */
    // Write address channel
    .AWVALID_MASTER_1 (ifu_to_arbiter_AWVALID),
    .AWREADY_MASTER_1 (ifu_to_arbiter_AWREADY),
    .AWADDR_MASTER_1  (ifu_to_arbiter_AWADDR),
    .AWID_MASTER_1    (ifu_to_arbiter_AWID),
    .AWLEN_MASTER_1   (ifu_to_arbiter_AWLEN),
    .AWSIZE_MASTER_1  (ifu_to_arbiter_AWSIZE),
    .AWBURST_MASTER_1 (ifu_to_arbiter_AWBURST),

    // Write data channel
    .WVALID_MASTER_1  (ifu_to_arbiter_WVALID),
    .WREADY_MASTER_1  (ifu_to_arbiter_WREADY),
    .WDATA_MASTER_1   (ifu_to_arbiter_WDATA),
    .WSTRB_MASTER_1   (ifu_to_arbiter_WSTRB),
    .WLAST_MASTER_1   (ifu_to_arbiter_WLAST),

    // Write response channel
    .BVALID_MASTER_1  (ifu_to_arbiter_BVALID),
    .BREADY_MASTER_1  (ifu_to_arbiter_BREADY),
    .BRESP_MASTER_1   (ifu_to_arbiter_BRESP),
    .BID_MASTER_1     (ifu_to_arbiter_BID),

    // Read address channel
    .ARVALID_MASTER_1 (ifu_to_arbiter_ARVALID),
    .ARREADY_MASTER_1 (ifu_to_arbiter_ARREADY),
    .ARADDR_MASTER_1  (ifu_to_arbiter_ARADDR),
    .ARID_MASTER_1    (ifu_to_arbiter_ARID),
    .ARLEN_MASTER_1   (ifu_to_arbiter_ARLEN),
    .ARSIZE_MASTER_1  (ifu_to_arbiter_ARSIZE),
    .ARBURST_MASTER_1 (ifu_to_arbiter_ARBURST),

    // Read data channel
    .RVALID_MASTER_1  (ifu_to_arbiter_RVALID),
    .RREADY_MASTER_1  (ifu_to_arbiter_RREADY),
    .RDATA_MASTER_1   (ifu_to_arbiter_RDATA),
    .RRESP_MASTER_1   (ifu_to_arbiter_RRESP),
    .RLAST_MASTER_1   (ifu_to_arbiter_RLAST),
    .RID_MASTER_1     (ifu_to_arbiter_RID),

    /* Master2 interface */
    // Write address channel
    .AWVALID_MASTER_2 (mem_to_arbiter_AWVALID),
    .AWREADY_MASTER_2 (mem_to_arbiter_AWREADY),
    .AWADDR_MASTER_2  (mem_to_arbiter_AWADDR),
    .AWID_MASTER_2    (mem_to_arbiter_AWID),
    .AWLEN_MASTER_2   (mem_to_arbiter_AWLEN),
    .AWSIZE_MASTER_2  (mem_to_arbiter_AWSIZE),
    .AWBURST_MASTER_2 (mem_to_arbiter_AWBURST),

    // Write data channel
    .WVALID_MASTER_2  (mem_to_arbiter_WVALID),
    .WREADY_MASTER_2  (mem_to_arbiter_WREADY),
    .WDATA_MASTER_2   (mem_to_arbiter_WDATA),
    .WSTRB_MASTER_2   (mem_to_arbiter_WSTRB),
    .WLAST_MASTER_2   (mem_to_arbiter_WLAST),

    // Write response channel
    .BVALID_MASTER_2  (mem_to_arbiter_BVALID),
    .BREADY_MASTER_2  (mem_to_arbiter_BREADY),
    .BRESP_MASTER_2   (mem_to_arbiter_BRESP),
    .BID_MASTER_2     (mem_to_arbiter_BID),

    // Read address channel
    .ARVALID_MASTER_2 (mem_to_arbiter_ARVALID),
    .ARREADY_MASTER_2 (mem_to_arbiter_ARREADY),
    .ARADDR_MASTER_2  (mem_to_arbiter_ARADDR),
    .ARID_MASTER_2    (mem_to_arbiter_ARID),
    .ARLEN_MASTER_2   (mem_to_arbiter_ARLEN),
    .ARSIZE_MASTER_2  (mem_to_arbiter_ARSIZE),
    .ARBURST_MASTER_2 (mem_to_arbiter_ARBURST),

    // Read data channel
    .RVALID_MASTER_2  (mem_to_arbiter_RVALID),
    .RREADY_MASTER_2  (mem_to_arbiter_RREADY),
    .RDATA_MASTER_2   (mem_to_arbiter_RDATA),
    .RRESP_MASTER_2   (mem_to_arbiter_RRESP),
    .RLAST_MASTER_2   (mem_to_arbiter_RLAST),
    .RID_MASTER_2     (mem_to_arbiter_RID),

    /* Arbiter <=> top level interface */
    // Write address channel
    .AWVALID_SLAVE_1  (io_master_awvalid),
    .AWREADY_SLAVE_1  (io_master_awready),
    .AWADDR_SLAVE_1   (io_master_awaddr),
    .AWID_SLAVE_1     (io_master_awid),
    .AWLEN_SLAVE_1    (io_master_awlen),
    .AWSIZE_SLAVE_1   (io_master_awsize),
    .AWBURST_SLAVE_1  (io_master_awburst),

    // Write data channel
    .WVALID_SLAVE_1   (io_master_wvalid),
    .WREADY_SLAVE_1   (io_master_wready),
    .WDATA_SLAVE_1    (io_master_wdata),
    .WSTRB_SLAVE_1    (io_master_wstrb),
    .WLAST_SLAVE_1    (io_master_wlast),

    // Write response channel
    .BVALID_SLAVE_1   (io_master_bvalid),
    .BREADY_SLAVE_1   (io_master_bready),
    .BRESP_SLAVE_1    (io_master_bresp),
    .BID_SLAVE_1      (io_master_bid),

    // Read address channel
    .ARVALID_SLAVE_1  (io_master_arvalid),
    .ARREADY_SLAVE_1  (io_master_arready),
    .ARADDR_SLAVE_1   (io_master_araddr),
    .ARID_SLAVE_1     (io_master_arid),
    .ARLEN_SLAVE_1    (io_master_arlen),
    .ARSIZE_SLAVE_1   (io_master_arsize),
    .ARBURST_SLAVE_1  (io_master_arburst),

    // Read data channel
    .RVALID_SLAVE_1   (io_master_rvalid),
    .RREADY_SLAVE_1   (io_master_rready),
    .RDATA_SLAVE_1    (io_master_rdata),
    .RRESP_SLAVE_1    (io_master_rresp),
    .RLAST_SLAVE_1    (io_master_rlast),
    .RID_SLAVE_1      (io_master_rid)
  );

  // ysyx_23060189_AXI_Lite_arbiter arbiter (
  //   // Global
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   /* Master1 interface */
  //   // Write address channel
  //   .AWVALID_MASTER_1(ifu_to_arbiter_AWVALID),
  //   .AWREADY_MASTER_1(ifu_to_arbiter_AWREADY),
  //   .AWADDR_MASTER_1(ifu_to_arbiter_AWADDR),
  //   .AWPROT_MASTER_1(ifu_to_arbiter_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_MASTER_1(ifu_to_arbiter_WVALID),
  //   .WREADY_MASTER_1(ifu_to_arbiter_WREADY),
  //   .WDATA_MASTER_1(ifu_to_arbiter_WDATA),
  //   .WSTRB_MASTER_1(ifu_to_arbiter_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_MASTER_1(ifu_to_arbiter_BVALID),
  //   .BREADY_MASTER_1(ifu_to_arbiter_BREADY),
  //   .BRESP_MASTER_1(ifu_to_arbiter_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_MASTER_1(ifu_to_arbiter_ARVALID),
  //   .ARREADY_MASTER_1(ifu_to_arbiter_ARREADY),
  //   .ARADDR_MASTER_1(ifu_to_arbiter_ARADDR),
  //   .ARPROT_MASTER_1(ifu_to_arbiter_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_MASTER_1(ifu_to_arbiter_RVALID),
  //   .RREADY_MASTER_1(ifu_to_arbiter_RREADY),
  //   .RDATA_MASTER_1(ifu_to_arbiter_RDATA),
  //   .RRESP_MASTER_1(ifu_to_arbiter_RRESP),
  //
  //   /* Master2 interface */
  //   // Write address channel
  //   .AWVALID_MASTER_2(mem_to_arbiter_AWVALID),
  //   .AWREADY_MASTER_2(mem_to_arbiter_AWREADY),
  //   .AWADDR_MASTER_2(mem_to_arbiter_AWADDR),
  //   .AWPROT_MASTER_2(mem_to_arbiter_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_MASTER_2(mem_to_arbiter_WVALID),
  //   .WREADY_MASTER_2(mem_to_arbiter_WREADY),
  //   .WDATA_MASTER_2(mem_to_arbiter_WDATA),
  //   .WSTRB_MASTER_2(mem_to_arbiter_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_MASTER_2(mem_to_arbiter_BVALID),
  //   .BREADY_MASTER_2(mem_to_arbiter_BREADY),
  //   .BRESP_MASTER_2(mem_to_arbiter_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_MASTER_2(mem_to_arbiter_ARVALID),
  //   .ARREADY_MASTER_2(mem_to_arbiter_ARREADY),
  //   .ARADDR_MASTER_2(mem_to_arbiter_ARADDR),
  //   .ARPROT_MASTER_2(mem_to_arbiter_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_MASTER_2(mem_to_arbiter_RVALID),
  //   .RREADY_MASTER_2(mem_to_arbiter_RREADY),
  //   .RDATA_MASTER_2(mem_to_arbiter_RDATA),
  //   .RRESP_MASTER_2(mem_to_arbiter_RRESP),
  //
  //   /* Arbiter <=> Xbar */
  //   // Write address channel
  //   .AWVALID_SLAVE_1(arbiter_to_xbar_AWVALID),
  //   .AWREADY_SLAVE_1(arbiter_to_xbar_AWREADY),
  //   .AWADDR_SLAVE_1(arbiter_to_xbar_AWADDR),
  //   .AWPROT_SLAVE_1(arbiter_to_xbar_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_SLAVE_1(arbiter_to_xbar_WVALID),
  //   .WREADY_SLAVE_1(arbiter_to_xbar_WREADY),
  //   .WDATA_SLAVE_1(arbiter_to_xbar_WDATA),
  //   .WSTRB_SLAVE_1(arbiter_to_xbar_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_SLAVE_1(arbiter_to_xbar_BVALID),
  //   .BREADY_SLAVE_1(arbiter_to_xbar_BREADY),
  //   .BRESP_SLAVE_1(arbiter_to_xbar_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_SLAVE_1(arbiter_to_xbar_ARVALID),
  //   .ARREADY_SLAVE_1(arbiter_to_xbar_ARREADY),
  //   .ARADDR_SLAVE_1(arbiter_to_xbar_ARADDR),
  //   .ARPROT_SLAVE_1(arbiter_to_xbar_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_SLAVE_1(arbiter_to_xbar_RVALID),
  //   .RREADY_SLAVE_1(arbiter_to_xbar_RREADY),
  //   .RDATA_SLAVE_1(arbiter_to_xbar_RDATA),
  //   .RRESP_SLAVE_1(arbiter_to_xbar_RRESP)
  // );

  // ysyx_23060189_Xbar Xbar(
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   /* Xbar <=> Arbiter */
  //   // Write address channel
  //   .AWVALID_SLAVE_1(arbiter_to_xbar_AWVALID),
  //   .AWREADY_SLAVE_1(arbiter_to_xbar_AWREADY),
  //   .AWADDR_SLAVE_1(arbiter_to_xbar_AWADDR),
  //   .AWPROT_SLAVE_1(arbiter_to_xbar_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_SLAVE_1(arbiter_to_xbar_WVALID),
  //   .WREADY_SLAVE_1(arbiter_to_xbar_WREADY),
  //   .WDATA_SLAVE_1(arbiter_to_xbar_WDATA),
  //   .WSTRB_SLAVE_1(arbiter_to_xbar_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_SLAVE_1(arbiter_to_xbar_BVALID),
  //   .BREADY_SLAVE_1(arbiter_to_xbar_BREADY),
  //   .BRESP_SLAVE_1(arbiter_to_xbar_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_SLAVE_1(arbiter_to_xbar_ARVALID),
  //   .ARREADY_SLAVE_1(arbiter_to_xbar_ARREADY),
  //   .ARADDR_SLAVE_1(arbiter_to_xbar_ARADDR),
  //   .ARPROT_SLAVE_1(arbiter_to_xbar_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_SLAVE_1(arbiter_to_xbar_RVALID),
  //   .RREADY_SLAVE_1(arbiter_to_xbar_RREADY),
  //   .RDATA_SLAVE_1(arbiter_to_xbar_RDATA),
  //   .RRESP_SLAVE_1(arbiter_to_xbar_RRESP),
  //
  //   /* Xbar <=> DSRAM */
  //   // Write address channel
  //   .AWVALID_SLAVE_DSRAM(xbar_to_dsram_AWVALID),
  //   .AWREADY_SLAVE_DSRAM(xbar_to_dsram_AWREADY),
  //   .AWADDR_SLAVE_DSRAM(xbar_to_dsram_AWADDR),
  //   .AWPROT_SLAVE_DSRAM(xbar_to_dsram_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_SLAVE_DSRAM(xbar_to_dsram_WVALID),
  //   .WREADY_SLAVE_DSRAM(xbar_to_dsram_WREADY),
  //   .WDATA_SLAVE_DSRAM(xbar_to_dsram_WDATA),
  //   .WSTRB_SLAVE_DSRAM(xbar_to_dsram_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_SLAVE_DSRAM(xbar_to_dsram_BVALID),
  //   .BREADY_SLAVE_DSRAM(xbar_to_dsram_BREADY),
  //   .BRESP_SLAVE_DSRAM(xbar_to_dsram_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_SLAVE_DSRAM(xbar_to_dsram_ARVALID),
  //   .ARREADY_SLAVE_DSRAM(xbar_to_dsram_ARREADY),
  //   .ARADDR_SLAVE_DSRAM(xbar_to_dsram_ARADDR),
  //   .ARPROT_SLAVE_DSRAM(xbar_to_dsram_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_SLAVE_DSRAM(xbar_to_dsram_RVALID),
  //   .RREADY_SLAVE_DSRAM(xbar_to_dsram_RREADY),
  //   .RDATA_SLAVE_DSRAM(xbar_to_dsram_RDATA),
  //   .RRESP_SLAVE_DSRAM(xbar_to_dsram_RRESP),
  //
  //   /* Xbar <=> UART */
  //   // Write address channel
  //   .AWVALID_SLAVE_UART(xbar_to_uart_AWVALID),
  //   .AWREADY_SLAVE_UART(xbar_to_uart_AWREADY),
  //   .AWADDR_SLAVE_UART(xbar_to_uart_AWADDR),
  //   .AWPROT_SLAVE_UART(xbar_to_uart_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_SLAVE_UART(xbar_to_uart_WVALID),
  //   .WREADY_SLAVE_UART(xbar_to_uart_WREADY),
  //   .WDATA_SLAVE_UART(xbar_to_uart_WDATA),
  //   .WSTRB_SLAVE_UART(xbar_to_uart_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_SLAVE_UART(xbar_to_uart_BVALID),
  //   .BREADY_SLAVE_UART(xbar_to_uart_BREADY),
  //   .BRESP_SLAVE_UART(xbar_to_uart_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_SLAVE_UART(xbar_to_uart_ARVALID),
  //   .ARREADY_SLAVE_UART(xbar_to_uart_ARREADY),
  //   .ARADDR_SLAVE_UART(xbar_to_uart_ARADDR),
  //   .ARPROT_SLAVE_UART(xbar_to_uart_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_SLAVE_UART(xbar_to_uart_RVALID),
  //   .RREADY_SLAVE_UART(xbar_to_uart_RREADY),
  //   .RDATA_SLAVE_UART(xbar_to_uart_RDATA),
  //   .RRESP_SLAVE_UART(xbar_to_uart_RRESP),
  //
  //   /* Xbar <=> CLINT */
  //   // Write address channel
  //   .AWVALID_SLAVE_CLINT(xbar_to_clint_AWVALID),
  //   .AWREADY_SLAVE_CLINT(xbar_to_clint_AWREADY),
  //   .AWADDR_SLAVE_CLINT(xbar_to_clint_AWADDR),
  //   .AWPROT_SLAVE_CLINT(xbar_to_clint_AWPROT),
  //
  //   // Write data channel
  //   .WVALID_SLAVE_CLINT(xbar_to_clint_WVALID),
  //   .WREADY_SLAVE_CLINT(xbar_to_clint_WREADY),
  //   .WDATA_SLAVE_CLINT(xbar_to_clint_WDATA),
  //   .WSTRB_SLAVE_CLINT(xbar_to_clint_WSTRB),
  //
  //   // Write response channel
  //   .BVALID_SLAVE_CLINT(xbar_to_clint_BVALID),
  //   .BREADY_SLAVE_CLINT(xbar_to_clint_BREADY),
  //   .BRESP_SLAVE_CLINT(xbar_to_clint_BRESP),
  //
  //   // Read address channel
  //   .ARVALID_SLAVE_CLINT(xbar_to_clint_ARVALID),
  //   .ARREADY_SLAVE_CLINT(xbar_to_clint_ARREADY),
  //   .ARADDR_SLAVE_CLINT(xbar_to_clint_ARADDR),
  //   .ARPROT_SLAVE_CLINT(xbar_to_clint_ARPROT),
  //
  //   // Read data channel
  //   .RVALID_SLAVE_CLINT(xbar_to_clint_RVALID),
  //   .RREADY_SLAVE_CLINT(xbar_to_clint_RREADY),
  //   .RDATA_SLAVE_CLINT(xbar_to_clint_RDATA),
  //   .RRESP_SLAVE_CLINT(xbar_to_clint_RRESP)
  // );

  // ysyx_23060189_AXI_Lite_slave xbar_to_uart_slave_interface (
  //   /* Slave <=> Slave interface */
  //   .ren(slave_to_uart_ren),
  //   .raddr(slave_to_uart_raddr),
  //   .rdata(slave_to_uart_rdata),
  //   .rvalid(slave_to_uart_rvalid),
  //
  //   .wen(slave_to_uart_wen),
  //   .waddr(slave_to_uart_waddr),
  //   .wdata(slave_to_uart_wdata),
  //   .wmask(slave_to_uart_wmask),
  //   .wdone(slave_to_uart_wdone),
  //
  //   /* Slave interface <=> Arbiter */
  //   // Global
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   // Write address channel
  //   .AWVALID(xbar_to_uart_AWVALID),
  //   .AWREADY(xbar_to_uart_AWREADY),
  //   .AWADDR(xbar_to_uart_AWADDR),
  //   .AWPROT(xbar_to_uart_AWPROT),
  //
  //   // Write data channel
  //   .WVALID(xbar_to_uart_WVALID),
  //   .WREADY(xbar_to_uart_WREADY),
  //   .WDATA(xbar_to_uart_WDATA),
  //   .WSTRB(xbar_to_uart_WSTRB),
  //
  //   // Write response channel
  //   .BVALID(xbar_to_uart_BVALID),
  //   .BREADY(xbar_to_uart_BREADY),
  //   .BRESP(xbar_to_uart_BRESP),
  //
  //   // Read address channel
  //   .ARVALID(xbar_to_uart_ARVALID),
  //   .ARREADY(xbar_to_uart_ARREADY),
  //   .ARADDR(xbar_to_uart_ARADDR),
  //   .ARPROT(xbar_to_uart_ARPROT),
  //
  //   // Read data channel
  //   .RVALID(xbar_to_uart_RVALID),
  //   .RREADY(xbar_to_uart_RREADY),
  //   .RDATA(xbar_to_uart_RDATA),
  //   .RRESP(xbar_to_uart_RRESP)
  // );

  // ysyx_23060189_AXI_Lite_slave xbar_to_clint_slave_interface (
  //   /* Slave <=> Slave interface */
  //   .ren(slave_to_clint_ren),
  //   .raddr(slave_to_clint_raddr),
  //   .rdata(slave_to_clint_rdata),
  //   .rvalid(slave_to_clint_rvalid),
  //
  //   .wen(slave_to_clint_wen),
  //   .waddr(slave_to_clint_waddr),
  //   .wdata(slave_to_clint_wdata),
  //   .wmask(slave_to_clint_wmask),
  //   .wdone(slave_to_clint_wdone),
  //
  //   /* Slave interface <=> Arbiter */
  //   // Global
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   // Write address channel
  //   .AWVALID(xbar_to_clint_AWVALID),
  //   .AWREADY(xbar_to_clint_AWREADY),
  //   .AWADDR(xbar_to_clint_AWADDR),
  //   .AWPROT(xbar_to_clint_AWPROT),
  //
  //   // Write data channel
  //   .WVALID(xbar_to_clint_WVALID),
  //   .WREADY(xbar_to_clint_WREADY),
  //   .WDATA(xbar_to_clint_WDATA),
  //   .WSTRB(xbar_to_clint_WSTRB),
  //
  //   // Write response channel
  //   .BVALID(xbar_to_clint_BVALID),
  //   .BREADY(xbar_to_clint_BREADY),
  //   .BRESP(xbar_to_clint_BRESP),
  //
  //   // Read address channel
  //   .ARVALID(xbar_to_clint_ARVALID),
  //   .ARREADY(xbar_to_clint_ARREADY),
  //   .ARADDR(xbar_to_clint_ARADDR),
  //   .ARPROT(xbar_to_clint_ARPROT),
  //
  //   // Read data channel
  //   .RVALID(xbar_to_clint_RVALID),
  //   .RREADY(xbar_to_clint_RREADY),
  //   .RDATA(xbar_to_clint_RDATA),
  //   .RRESP(xbar_to_clint_RRESP)
  // );

  // ysyx_23060189_UART uart (
  //   /* Slave <=> Slave interface */
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   .ren(slave_to_uart_ren),
  //   .raddr(slave_to_uart_raddr),
  //   .rdata(slave_to_uart_rdata),
  //   .rvalid(slave_to_uart_rvalid),
  //
  //   .wen(slave_to_uart_wen),
  //   .waddr(slave_to_uart_waddr),
  //   .wdata(slave_to_uart_wdata),
  //   .wmask(slave_to_uart_wmask),
  //   .wdone(slave_to_uart_wdone)
  // );

  // ysyx_23060189_CLINT clint (
  //   /* Slave <=> Slave interface */
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   .ren(slave_to_clint_ren),
  //   .raddr(slave_to_clint_raddr),
  //   .rdata(slave_to_clint_rdata),
  //   .rvalid(slave_to_clint_rvalid),
  //
  //   .wen(slave_to_clint_wen),
  //   .waddr(slave_to_clint_waddr),
  //   .wdata(slave_to_clint_wdata),
  //   .wmask(slave_to_clint_wmask),
  //   .wdone(slave_to_clint_wdone)
  // );

  // 数据存储器
  // ysyx_23060189_DSRAM dsram (
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //   // read
  //   .ren(slave_to_dsram_ren),
  //   .raddr(slave_to_dsram_raddr),
  //   .rdata(slave_to_dsram_rdata),
  //   .rvalid(slave_to_dsram_rvalid),
  //   // write
  //   .wen(slave_to_dsram_wen),
  //   .waddr(slave_to_dsram_waddr),
  //   .wdata(slave_to_dsram_wdata),
  //   .wmask(slave_to_dsram_wmask),
  //   .wdone(slave_to_dsram_wdone)
  // );

  // // master1 interface: IFU <=> DSRAM
  // ysyx_23060189_AXI_Lite_master ifu_to_arbiter_master_interface(
  //   /* Master <=> Master interface */
  //   .ren(ifu_to_master_ren),
  //   .raddr(ifu_to_master_raddr),
  //   .rdata(ifu_to_master_rdata),
  //   .rvalid(ifu_to_master_rvalid),
  //
  //   .wen(ifu_to_master_wen),
  //   .waddr(ifu_to_master_waddr),
  //   .wdata(ifu_to_master_wdata),
  //   .wmask(ifu_to_master_wmask),
  //   .wdone(ifu_to_master_wdone),
  //
  //   /* Master interface <=> Slave interface*/
  //   // Global
  //   .ACLK(clock),
  //   .ARESETn(~reset),
  //
  //   // Write address channel
  //   .AWVALID(ifu_to_arbiter_AWVALID),
  //   .AWREADY(ifu_to_arbiter_AWREADY),
  //   .AWADDR(ifu_to_arbiter_AWADDR),
  //   .AWPROT(ifu_to_arbiter_AWPROT),
  //
  //   // Write data channel
  //   .WVALID(ifu_to_arbiter_WVALID),
  //   .WREADY(ifu_to_arbiter_WREADY),
  //   .WDATA(ifu_to_arbiter_WDATA),
  //   .WSTRB(ifu_to_arbiter_WSTRB),
  //
  //   // Write response channel
  //   .BVALID(ifu_to_arbiter_BVALID),
  //   .BREADY(ifu_to_arbiter_BREADY),
  //   .BRESP(ifu_to_arbiter_BRESP),
  //
  //   // Read address channel
  //   .ARVALID(ifu_to_arbiter_ARVALID),
  //   .ARREADY(ifu_to_arbiter_ARREADY),
  //   .ARADDR(ifu_to_arbiter_ARADDR),
  //   .ARPROT(ifu_to_arbiter_ARPROT),
  //
  //   // Read data channel
  //   .RVALID(ifu_to_arbiter_RVALID),
  //   .RREADY(ifu_to_arbiter_RREADY),
  //   .RDATA(ifu_to_arbiter_RDATA),
  //   .RRESP(ifu_to_arbiter_RRESP)
  // );

  // ifu <=> AXI4 Bus
  ysyx_23060189_AXI4_master ifu_to_axi4_bus (
    /* Master <=> Master interface */
    .ren     (ifu_to_master_ren),
    .raddr   (ifu_to_master_raddr),
    .arsize  (ifu_to_master_arsize),
    .rdata   (ifu_to_master_rdata),
    .rvalid  (ifu_to_master_rvalid),

    .wen     (ifu_to_master_wen),
    .waddr   (ifu_to_master_waddr),
    .wdata   (ifu_to_master_wdata),
    .wmask   (ifu_to_master_wmask),
    .awsize  (ifu_to_master_awsize),
    .wdone   (ifu_to_master_wdone),

    /* Master interface <=> Arbiter */
    // Global
    .ACLK    (clock),
    .ARESETn (~reset),

    // Write address channel
    .AWVALID (ifu_to_arbiter_AWVALID),
    .AWREADY (ifu_to_arbiter_AWREADY),
    .AWADDR  (ifu_to_arbiter_AWADDR),
    .AWID    (ifu_to_arbiter_AWID),
    .AWLEN   (ifu_to_arbiter_AWLEN),
    .AWSIZE  (ifu_to_arbiter_AWSIZE),
    .AWBURST (ifu_to_arbiter_AWBURST),

    // Write data channel
    .WVALID  (ifu_to_arbiter_WVALID),
    .WREADY  (ifu_to_arbiter_WREADY),
    .WDATA   (ifu_to_arbiter_WDATA),
    .WSTRB   (ifu_to_arbiter_WSTRB),
    .WLAST   (ifu_to_arbiter_WLAST),

    // Write response channel
    .BVALID  (ifu_to_arbiter_BVALID),
    .BREADY  (ifu_to_arbiter_BREADY),
    .BRESP   (ifu_to_arbiter_BRESP),
    .BID     (ifu_to_arbiter_BID),

    // Read address channel
    .ARVALID (ifu_to_arbiter_ARVALID),
    .ARREADY (ifu_to_arbiter_ARREADY),
    .ARADDR  (ifu_to_arbiter_ARADDR),
    .ARID    (ifu_to_arbiter_ARID),
    .ARLEN   (ifu_to_arbiter_ARLEN),
    .ARSIZE  (ifu_to_arbiter_ARSIZE),
    .ARBURST (ifu_to_arbiter_ARBURST),

    // Read data channel
    .RVALID  (ifu_to_arbiter_RVALID),
    .RREADY  (ifu_to_arbiter_RREADY),
    .RDATA   (ifu_to_arbiter_RDATA),
    .RRESP   (ifu_to_arbiter_RRESP),
    .RLAST   (ifu_to_arbiter_RLAST),
    .RID     (ifu_to_arbiter_RID)
  );

  ysyx_23060189_IFU #(`ysyx_23060189_DATA_W) ifu (
    .clk         (clock),
    .rst         (reset),
    .done        (done),
    // data: WBU <=> IFU
    .wb_PC_sel   (wb_PC_sel),
    .wb_wb_sel   (wb_wb_sel),
    .wb_wb_en    (wb_wb_en),
    .wb_br_taken (wb_br_taken),
    .wb_csr_out  (wb_csr_out),
    .wb_Alu_out  (wb_Alu_out),
    .wb_wb_addr  (wb_wb_addr),
    .wb_rd_data  (wb_rd_data),
    .wb_valid    (wb_valid),
    .if_ready    (if_ready),
    // data: IFU <=> IDU
    .if_inst     (if_inst),
    .if_pc       (if_pc),
    .if_wb_addr  (if_wb_addr),
    .if_rs1_data (if_rs1_data),
    .if_rs2_data (if_rs2_data),
    .if_valid    (if_valid),
    .de_ready    (de_ready),
    /* IFU <=> Master interface */
    .ACLK        (clock),
    .ARESETn     (~reset),
    // read
    .ren         (ifu_to_master_ren),
    .raddr       (ifu_to_master_raddr),
    .arsize      (ifu_to_master_arsize),
    .rdata       (ifu_to_master_rdata),
    .rvalid      (ifu_to_master_rvalid),

    // write
    .wen         (ifu_to_master_wen),
    .waddr       (ifu_to_master_waddr),
    .wdata       (ifu_to_master_wdata),
    .wmask       (ifu_to_master_wmask),
    .awsize      (ifu_to_master_awsize),
    .wdone       (ifu_to_master_wdone)
  );

  ysyx_23060189_IDU #(`ysyx_23060189_DATA_W) idu (
    // data: IFU <=> IDU
    .if_inst     (if_inst),
    .if_pc       (if_pc),
    .if_wb_addr  (if_wb_addr),
    .if_rs1_data (if_rs1_data),
    .if_rs2_data (if_rs2_data),
    .if_valid    (if_valid),
    .de_ready    (de_ready),
    // data: IDU <=> EXU
    .de_inst     (de_inst),
    .de_pc       (de_pc),
    .de_PC_sel   (de_PC_sel),
    .de_Imm_sel  (de_Imm_sel),
    .de_Alu_op   (de_Alu_op),
    .de_st_type  (de_st_type),
    .de_ld_type  (de_ld_type),
    .de_br_type  (de_br_type),
    .de_A_sel    (de_A_sel),
    .de_B_sel    (de_B_sel),
    .de_wb_sel   (de_wb_sel),
    .de_csr_cmd  (de_csr_cmd),
    .de_wb_en    (de_wb_en),
    .de_wb_addr  (de_wb_addr),
    .de_rs1_data (de_rs1_data),
    .de_rs2_data (de_rs2_data),
    .de_valid    (de_valid),
    .ex_ready    (ex_ready)
  );

  ysyx_23060189_EXU #(`ysyx_23060189_DATA_W) exu (
    // data: IDU <=> EXU
    .de_inst     (de_inst),
    .de_pc       (de_pc),
    .de_PC_sel   (de_PC_sel),
    .de_Imm_sel  (de_Imm_sel),
    .de_Alu_op   (de_Alu_op),
    .de_st_type  (de_st_type),
    .de_ld_type  (de_ld_type),
    .de_br_type  (de_br_type),
    .de_A_sel    (de_A_sel),
    .de_B_sel    (de_B_sel),
    .de_wb_sel   (de_wb_sel),
    .de_csr_cmd  (de_csr_cmd),
    .de_wb_en    (de_wb_en),
    .de_wb_addr  (de_wb_addr),
    .de_rs1_data (de_rs1_data),
    .de_rs2_data (de_rs2_data),
    .de_valid    (de_valid),
    .ex_ready    (ex_ready),
    // data: EXU <=> MEU
    .ex_inst     (ex_inst),
    .ex_pc       (ex_pc),
    .ex_PC_sel   (ex_PC_sel),
    .ex_st_type  (ex_st_type),
    .ex_ld_type  (ex_ld_type),
    .ex_wb_sel   (ex_wb_sel),
    .ex_csr_cmd  (ex_csr_cmd),
    .ex_wb_en    (ex_wb_en),
    .ex_br_taken (ex_br_taken),
    .ex_Alu_out  (ex_Alu_out),
    .ex_wb_addr  (ex_wb_addr),
    .ex_rs2_data (ex_rs2_data),
    .ex_valid    (ex_valid),
    .me_ready    (me_ready)
  );

  ysyx_23060189_MEU #(`ysyx_23060189_DATA_W) meu (
    .clk         (clock),
    .rst         (reset),
    // data: EXU <=> MEU
    .ex_inst     (ex_inst),
    .ex_pc       (ex_pc),
    .ex_PC_sel   (ex_PC_sel),
    .ex_st_type  (ex_st_type),
    .ex_ld_type  (ex_ld_type),
    .ex_wb_sel   (ex_wb_sel),
    .ex_csr_cmd  (ex_csr_cmd),
    .ex_wb_en    (ex_wb_en),
    .ex_br_taken (ex_br_taken),
    .ex_Alu_out  (ex_Alu_out),
    .ex_wb_addr  (ex_wb_addr),
    .ex_rs2_data (ex_rs2_data),
    .ex_valid    (ex_valid),
    .me_ready    (me_ready),
    // data: MEU <=> WBU
    .me_inst     (me_inst),
    .me_pc       (me_pc),
    .me_PC_sel   (me_PC_sel),
    .me_wb_sel   (me_wb_sel),
    .me_csr_cmd  (me_csr_cmd),
    .me_wb_en    (me_wb_en),
    .me_br_taken (me_br_taken),
    .me_Alu_out  (me_Alu_out),
    .me_wb_addr  (me_wb_addr),
    .me_rd_data  (me_rd_data),
    .me_valid    (me_valid),
    .wb_ready    (wb_ready),
    // data:MEU <=> MEM
    .meu_valid   (meu_valid),
    .addr        (mem_addr),
    .st_type     (st_type),
    .ld_type     (ld_type),
    .wr_data     (wr_data),
    .rd_data     (rd_data),
    .mem_valid   (mem_valid)
  );

  ysyx_23060189_WBU #(`ysyx_23060189_DATA_W) wbu (
    .clk         (clock),
    .rst         (reset),
    // data: MEU <=> WBU
    .me_inst     (me_inst),
    .me_pc       (me_pc),
    .me_PC_sel   (me_PC_sel),
    .me_wb_sel   (me_wb_sel),
    .me_csr_cmd  (me_csr_cmd),
    .me_wb_en    (me_wb_en),
    .me_br_taken (me_br_taken),
    .me_Alu_out  (me_Alu_out),
    .me_wb_addr  (me_wb_addr),
    .me_rd_data  (me_rd_data),
    .me_valid    (me_valid),
    .wb_ready    (wb_ready),
    // data: WBU <=> IFU
    .wb_PC_sel   (wb_PC_sel),
    .wb_wb_sel   (wb_wb_sel),
    .wb_wb_en    (wb_wb_en),
    .wb_br_taken (wb_br_taken),
    .wb_csr_out  (wb_csr_out),
    .wb_Alu_out  (wb_Alu_out),
    .wb_wb_addr  (wb_wb_addr),
    .wb_rd_data  (wb_rd_data),
    .wb_valid    (wb_valid),
    .if_ready    (if_ready)
  );

endmodule
